`timescale 1ns / 1ns

module img_test0;

reg rst;
reg clk;

always #5 clk <= ~clk;

wire signed [15:0] x[2:0];
wire signed [15:0] y[2:0];
wire [15:0] z[2:0];
reg boot;

wire enable;

assign x[0] = 16'sd0, x[1] = 16'sd10, x[2] = 16'sd60;
assign y[0] = 16'sd0, y[1] = 16'sd45, y[2] = 16'sd20;
assign z[0] = 16'd0, z[1] = 16'd0, z[2] = 16'd0;

img_sche sche(
	.rst(rst), .clk(clk),
	.x(x), .y(y), .z(z),
	.boot(boot),
	.enable(enable)
);

initial begin
    $dumpfile("img_test0.vcd");
    $dumpvars(0, img_test0);
end

integer img_file;
integer i, j;

wire signed [31:0] img_x = 32'sd64;
wire signed [31:0] img_y = 32'sd64;

wire[31:0] img_size = img_x * img_y * 3;

initial begin
    clk <= 1'b0;
    rst <= 1'b1;
    #1;
    rst <= 1'b0;
    #1;
    rst <= 1'b1;
    #3;
    boot = 1'b1;
    @(negedge enable);

    img_file = $fopen("out.bmp", "wb");
    $fwrite(img_file, "BM%u%u%u", 14, 0, 54);
    $fwrite(img_file, "%u%u%u%u%u%u%u%u%u%u",
        40, img_x, img_y, {16'd24, 16'd1}, 0, img_size, 0, 0, 0, 0);

    `include "a.v"

    $fclose(img_file);

    $finish;
end

endmodule